Re: [PATCH] add delay between port write and port read

From: Mikulas Patocka (mpatocka@xxxxxxxxxx)
Date: Tue Feb 19 2019 - 12:36:07 EST




On Tue, 19 Feb 2019, Maciej W. Rozycki wrote:

> On Tue, 19 Feb 2019, Arnd Bergmann wrote:
>
> > We clearly need this patch, but I assumed the alpha maintainers would pick
> > it up, not me. I merged the original changes since they were cross-architecture,
> > but I don't normally take patches for a particular architecture through the
> > asm-generic tree (or the soc tree for that matter).
>
> As I say, shouldn't the barrier be in `iowriteX' instead? I don't
> suppose these are allowed to be weakly ordered.
>
> Maciej

iowriteX is for memory-mapped I/O, out[bwl] is for I/O ports.

If someone finds a problem with memory-mapped device, he can add the
barier there.

Mikulas