Re: [PATCH] add delay between port write and port read

From: Mikulas Patocka (mpatocka@xxxxxxxxxx)
Date: Wed Feb 27 2019 - 12:05:00 EST

On Tue, 26 Feb 2019, Linus Torvalds wrote:

> On Tue, Feb 26, 2019 at 10:38 AM Will Deacon <will.deacon@xxxxxxx> wrote:
> >
> > That makes sense to me for this Alpha-specific case, but in general I
> > don't think we require that I/O accesses to different endpoints are
> > ordered with respect to each other, which was implied by one of Maciej's
> > examples. e.g.
> >
> > writeb(0x42, &foo_mmio_reg);
> > readb(&bar_mmio_reg);
> If they are the same device (just different data ports), I'd
> *definitely* expect them to be ordered.
> We have tons of code that depends on that. Almost every driver out
> there, in fact.
> So we need the mb() on alpha to guarantee the access ordering on the
> CPU side, and then PCI itself ends up guaranteeing that accesses to
> the same device will remain ordered outside the CPU.
> Agreed?
> Linus

Should "writeb_relaxed" on Alpha also use the barrier?

The understanding is that readX_relaxed and writeX_relaxed are ordered
with other accesses to the same PCI device. If Alpha doesn't gaurantee
that, they should use barriers too.