Re: [PATCH] add delay between port write and port read

From: Sinan Kaya (Okaya@xxxxxxxxxx)
Date: Wed Feb 27 2019 - 12:24:25 EST

On 2/27/2019 12:12 PM, Mikulas Patocka wrote:
It used to be like that and it worked.

Then, commits cd0e00c106722eca40b38ebf11cf134c01901086 and
92d7223a74235054f2aa7227d207d9c57f84dca0 came.

These commits claim that they changed the code to be consistent with the
specification (now we have barrier after ioread and before iowrite). But
they broke serial port and RTC on my Alpha machine.

A barrier before write is needed to ensure that memory operations done
are visible to the hardware before you send a write command.

Barrier after read is needed to ensure that if you read a memory
location after register read, memory contents are coherent.

What we missed is the fact that alpha reorders accesses across two
register accesses. This is guaranteed in other architectures.

To satisfy this, you need something like

register write
register read