Re: [PATCH] add delay between port write and port read

From: Maciej W. Rozycki (macro@xxxxxxxxxxxxxx)
Date: Wed Feb 27 2019 - 13:12:21 EST

On Wed, 27 Feb 2019, Sinan Kaya wrote:

> What we missed is the fact that alpha reorders accesses across two
> register accesses. This is guaranteed in other architectures.

Not for MIPS either.