Re: [PATCH] add delay between port write and port read
From: Linus Torvalds (torvalds@xxxxxxxxxxxxxxxxxxxx)
Date: Fri Mar 01 2019 - 12:47:47 EST
On Fri, Mar 1, 2019 at 9:33 AM Will Deacon <will.deacon@xxxxxxx> wrote:
> I'd expect accesses to device RAM to use something like ioremap_wc() if
> possible. In that case, the ordering of accesses is weakened by the
> underlying memory type in the page tables, but we're not yet at the point
> where we've figured out the portable semantics in this case. I plan to
> look at that once we've nailed normal ioremap()!
The case that matters most from a performance standpoint is
traditionally stupid framebuffer accesses, and the fb layer has
basically standardized this:
#define fb_writel __raw_writel
together with various fb drivers then using "wmb()" etc for ordering
for the non-framebuffer effects.
So that would seem what an architecture implementation should _aim_
for: having various "ioremap_xyz()" for setting the
PCIe/system/whatever controller level ordering, and then using the
"__raw_xyz()" accessors for unordered CPU accesses.