Re: [PATCH] add delay between port write and port read

From: Linus Torvalds (torvalds@xxxxxxxxxxxxxxxxxxxx)
Date: Fri Mar 01 2019 - 13:09:55 EST


On Fri, Mar 1, 2019 at 10:03 AM Maciej W. Rozycki <macro@xxxxxxxxxxxxxx> wrote:
>
> Well, `__raw_*' accessors are never byte-swapped, not at least with the
> MIPS port, making them a tad cumbersome for a driver that has no interest
> in paying attention to any endianness mismatch between the CPU bus and the
> device's peripheral bus.

Well, the people who want ultimate performance and not worry about
access ordering almost always _also_ want to handle byte ordering
manually.

Because quite often you don't want any extra byte ordering because
you've moving things around anyway (ie you're copying from the device
to memory or similar, and switching to little-endian in between would
just mean that you have to switch back for the memory write anyway).

Does it make things more complicated for a driver when it has to care
about byte ordering and not just say "PCI is always little-endian"?
Yes. But if you want simple, you shouldn't be doing the unordered
accesses.

Linus