Re: [PATCH] add delay between port write and port read

From: Maciej W. Rozycki (macro@xxxxxxxxxxxxxx)
Date: Fri Mar 01 2019 - 14:13:42 EST

On Fri, 1 Mar 2019, Linus Torvalds wrote:

> So that would seem what an architecture implementation should _aim_
> for: having various "ioremap_xyz()" for setting the
> PCIe/system/whatever controller level ordering, and then using the
> "__raw_xyz()" accessors for unordered CPU accesses.

What do we do WRT straight-through vs byte-swapping properties of these

For the record: we do need to have straight-through accessors for
endianness-agnostic peripherals. This is the case for example with SOC
devices that have plenty of I/O onchip that are always accessed natively
regardless of the endianness of the external bus.

E.g. with the Broadcom SiByte BCM1250 SOC we have a whole lot of devices
onchip (including a pair of MIPS64 CPU cores), and then PCI and HT
endpoints, and the SOC's endianness is configurable at reset. The
endianness selected only applies to the external bus, affecting external
data lanes: in the big-endian case there's a choice between matching byte
lanes or bit lanes by using one of the two MMIO physical address spaces
that apply either of these policies; in the little-endian case access is
pass-through of course. Consequently we have to use straight-through
accessors for onchip devices and byte-swapped ones for PCI/HT devices.