Re: [PATCH] add delay between port write and port read
From: Maciej W. Rozycki (macro@xxxxxxxxxxxxxx)
Date: Fri Mar 01 2019 - 19:30:03 EST
On Fri, 1 Mar 2019, Linus Torvalds wrote:
> > Without that, using __raw_xyz() to copy between RAM and
> > buffers in PCI memory space is broken, as you said, but the
> > assumption would be broken on certain older machines that
> > do a hardware endian swap by swizzling the address lines rather
> > than swapping bytes on the data bus.
> Honestly, there's no way we can ever fix that.
Well, (: the good news is we actually have it covered in the MIPS port
already, with the interfaces I described in the other e-mail. We have had
it for some 15 years now, ever since we got the ATA PIO stuff covered.
So all that we need is to agree upon names so that everyone does not come
up with their own ones, write them down somewhere, and let individual port
maintainers sort it out as they deem necessary. This way we have a
solution available, but don't have to do anything. Win-win.
> Because no new CPU's will ever be designed where the byte order isn't
> little-endian, and nobody will ever make those broken "we'll do random
> things in hardware to worfk around the fact that we're doing crazy
> things" machines.
Even better then: the trasformation will be trivial, i.e. pass-through,
so all the new CPU stuff will merely alias all the accessor variants to
each other. Which means we can put all that as a bunch of #defines in
include/asm-generic/io.h and forget about it.