I can fill in some inmformation that might help you fix the problem:
most PCI systems include a PCI->ISA or a PCI->EISA bridge. The bridge
contains lots of the IBM PC/AT baggage traditionally found in the CPU
support chipset ie the cascaded 8259s (interrupt controllers) the 2 8237
(DMA controllers) the 8254 (timer) etc.
many PCI systems handle interrupts by routing PCI interrupt requests
into channels of the 8259s. Now, this is a rather sub-optimal scheme
(and, IMO, you can blame the PCI bus committee for really wimping out
by not defining interrupts better) but it means that, for handling
PCI interrupts, as well as for handling interrupts from <american
accent on> legacy I/O devices <off> you need to talk to the cascaded
8259s.
The 8259 drives an interrupt vector onto the bus during an interrupt
acknowledge cycle. The consequence of chaining 2 devices is that you
must generate 2 intack cycles (by some magic they then both work out
what to do).
An 80386 CPU (for example) automatically generates a double intack. The
host-to-pci bridge swallows one of them and propogates a single intack
on the PCI bus. The PCI->ISA (or EISA) bridge regenerates the second
cycle to satisfy the 8259 requirements. The 8259 drives a vector on
the bus and this is propogated back to the CPU which goes to the appropriate
memory vector and thence to its Interrupt Service Routine.
No current Alpha implementations have such baggage as intack cycles. In
order to interface to arcane obsolete hardware like the ISA bus, there
is some logic that causes a CPU read from a certain memory address to
generate an intack cycle. When the interrupt controller returns its
vector this is simply received by the CPU as data, and it can use it
as a jump table (or whatever) index.
So, you need to know the memory address on Jensen that allows you
to read the interrupt vector. That's the magic number I can't help
you with (but at least you'll know how to use it when you get it - you
should be able to use it in exactly the same way as the APECs does)
Neal.
European Semiconductor Applications Engineering,
Reading, England.