Example:
Mar 26 23:37:41 simba kernel: X(200): unaligned trap at 000000012004b6f0: 00000001401c6bc2 28 1
Mar 26 23:37:41 simba kernel: X(200): unaligned trap at 000000012004b6f0: 00000001401c6bc6 28 1
Is it "normal" and can I configure the kernel not to report unaligned
accesses?
Another question concernes cache:
The Cache RAMs I've purchased are to slow. Although they are 15ns marked
parts they don't run in the 15ns configuration and they show too many
ECC errors in the 20ns configuration. (I'm using a Noname/233MHz with
1 MB of cache).
Question: Is it a good idea to reprogram the cache timing register
in the MILO to values that meet better the requirements of my cache?
(Dave?) Does the current MILO any reprogramming of the memory controller registers?
Thanks for your comments.
Bjoern