On Mon, Jan 24, 2000 at 04:54:38PM -0800, Larry McVoy wrote:
> : OK, if you have an n-way SMP box, then you have n processors with n (local)
> : caches sharing a single block of main system memory. If you then run a
> : threaded program (like a renderer) with a thread per processor, you wind up
> : with n threads all looking at a single block of shared memory - right?
>
> Yes. A really good reference for all of this, at the sort of accessable
> and general level, is ``Computer Architecture, A Quantitative Approach''
> by Patterson and Hennessy, ISBN 1-55860-329-8. I have the second edition
> which was updated in '96. It's an excellent book and think that if all
> the members of this list read it and understood it, that would be of
> enormous benefit. It's a hardware book, but I'm of the school that says
> OS people are part hardware people and should have more than a passing
> understanding of hardware.
>
---end quoted text---
Hardware constrains the OS, so your view is surely correct. Any ideas how
the IA-64 impacts this discussion? A cursory look into the IA-64 Application
Developer's Architecture Guide is quite interesting. I haven't seen any
reference to SMP issues addressed in there. Is there any other source of
technical descriptions of the IA-64 hardware out there yet?
-- ---- Karen Shaeffer Neuralscape; (831) 426-8547 Santa Cruz, Ca. 95060 shaeffer@neuralscape.com http://www.neuralscape.com -------------------------------------------------------- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
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