BTW, I was the author that Rik couldn't remember of the original patch.
> > > + cachesize = 16; /* Pentiums, 2x8kB cache */
I've got a somewhat nicer patch that makes the model-specific
code in setup.c give us reasonable cache sizes most of the time.
> > > + bandwidth = 100;
...
> > Is the bandwidth from L1 to L2 on a Pentium really only 100 MB/sec?
roughly. it depends on whether this is socket7 ("PC66") or super7
(PC100, which is more like 150 MB/s). but the bandwidth bottleneck
on P5-class CPUs is the lame protocol at the socket, not cache or ram.
> Then again, this 100 MB/sec is just a wild guess, I'd be very
> much interested in some more educated numbers :)
I just did some measurements. for PC66, reads are around 100 MB/s,
and writes are only around 80 MB/s. I don't have a super7 system
handy at the moment.
people might be wondering why this stuff matters. well, there are some
performance problems with somewhat obscure machines (such as P5 SMP,
and, for that matter, sparc SMP (not sparc64)). but more important
is that knowing this value, along with a task's average timeslice usage,
should let even the uniprocessor scheduler do a better job.
regards, mark hahn.
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