On Tue, 15 Feb 2000, Richard B. Johnson wrote:
> Once programmed, there is no 'default vector'. The upper 5 bits of the
> vector are set in ICW2. If there are no interrupt requests pending, there
> are no vectors. Period.
Go read the datasheet.
> INTA Cycles come from the CPUs, not from the controller. If the
> CPUs were to generate such an ACK, without a coresponding request,
> the CPUs are broken. The controllers were of course not designed
A CPU generates INTA cycles for whatever interrupt requests it receives
provided dispensing of them is enabled. I doesn't check (how would it?)
whether a request comes from an 8259A or from another chip. It's surely
not right for INTA cycles to arrive at an 8259A if it's not an originator
of the IRQ yet Intel MP systems give you the ability to be configured in
such a way. The 8259A has to deal somehow with this situation and someone
might actually make some use of such a setup (i.e. one does not have to
treat chips religiously and configure them only into the blessed by the
manufacturer mode -- digital chips are just a bunch of logic gates which
may be configured in any way the hardware dependencies allow).
> to control two or more CPUs. For this reason, the board vendors do
> not feed the INT output to all the CPUs in parallel, they select
> each one in turn through a ripple-counter. This has the unfortunate
> consequence of missing interrupts until all the CPUs have been
> initialized. It also means that a dual-CPU SMP machine that was not
> properly hardware-reset (i.e. warm-boot), may miss every-other interrupt
> upon startup.
Intel MP systems work differently. Go read datasheets.
> You can simulate the response to an INTA (from the CPU) by setting
> the D2 bit in OCW3. It sets the highest requesting level in the
> in-service register and generates the vector that would be put
> on the address-lines for the vectored interrupt. On the next read
> the data returned will have the value D0-D2 of the interrupt request.
Guess what vector is put in this polling mode if no IRQs are pending...
> You don't have to send a physical INTA to the device(s), possibly
> killing your system. If the IR bits are all masked off, you will
> note that no such vector is generated. This shows that there is
> no "default vector".
Go read the datasheet.
> All this information is available in a book written by Lewis C.
> Eggebrecht, "Interfacing to the IBM Personal Computer", Howard W.
> Sams, Inc. ISBN 0-672-22027-X. He designed the first IBM PCs and
> the System 23. This is an "Old book, circa 1983" , but so is
> the 8259A.
Given how cluelessly was the IBM PC designed I wouldn't say its designers
had comprehensive knowledge on ICs used as its components.
> Reference to these "original works" should help reduce the amount
> of folklore associated with the devices used in the PC machines.
Note these are secondary works. Intel's datasheets are the original
ones.
> ALL IRQ inputs to the 8259A are latched. This is how it is able to
> remember the inputs so the programmed priority can work.
See the input circuitry diagram in the datasheet. Although there is a D
latch at the input, it's only used as an edge-detect logic in the
edge-triggered mode -- it's set upon a rising edge and reset upon a
falling edge, an INTA cycle or the ICW1 command.
> Once an interrupt-request line remains true for the required setup
> time, that input bit is latched. The physical device can 'buzz', deassert
> its request or do whatever it wants. The fact that an interrupt request
> occurred is sufficient for the controller to 'remember' it for all time.
Hmm, I guess you are writing of some other interrupt controller.
> It forgets it only when an EOI code is sent to the controller.
> There are two, 0x20 is non-specific and 0x60|int_no is specific.
> At this time, if the LTIM bit in the initialization register was not
> set, the input latch is reset.
You refer to ISR not to IRR, for sure. Go read the datasheets.
> The original 8259 was not designed for level-triggering, in fact
> it was designed for use with 8085. It has a bit in ICW4 to select
For 8080, actually.
> the 8085 or the 8088 mode. The 'A' version and subsequent CMOS versions
> provided a LTIM bit in the initialization register, ICW1 (bit 3). The
> function of this bit is to prevent resetting the input latch when an EOI
> (specific or non-specific) if sent to the device, IF the interrupt request
> line is still true. This has the effect of allowing a level to be
> detected. With this, multiple interrupt requests may be ORed into the same
> IRQ line.
You are writing of an INTA cycle for sure.
Please don't bother to comment on this mail -- there is no point in
negating facts. Unless you are writing of something else than Intel
8259A. In this case please state clearly what IC you are writing of.
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