On Thu, 17 Feb 2000, Charles Turner, Ph.D. wrote:
> > > It forgets it only when an EOI code is sent to the controller.
> > > There are two, 0x20 is non-specific and 0x60|int_no is specific.
> > > At this time, if the LTIM bit in the initialization register was not
> > > set, the input latch is reset.
> >
> > You refer to ISR not to IRR, for sure. Go read the datasheets.
>
> No. The in-service latch is what Johnson was refering to and, is
> in fact, the memory of the chip.
So we agree -- ISR is the in-service latch. But Richard wrote of the
input latch which must be the interrupt request latch, i.e. the IRR bit.
ISR is not at the input.
> > > The original 8259 was not designed for level-triggering, in fact
> > > it was designed for use with 8085. It has a bit in ICW4 to select
> >
> > For 8080, actually.
>
> No, the 8080 could not use vectored interrupts. The 8085 was correctly
> shown.
This is why the original 8259 as well as the 8259A in the 8080/85 mode
issues an 8080 "call" opcode during the first INTA cycle as well as a
two-byte long argument to "call" during the next two INTA cycles (for a
total of three INTA cycles). Actually 8080 issues as many INTA cycles as
necessary for a whole instruction fetch, e.g. if you supply is with a
single-byte "rst<x>" (where <x> is 0 to 7) opcode it will only issue a
single INTA cycle. It is possible to supply opcodes other than "call" or
"rst<x>" to 8080 but I haven't heard of any real implementation exploiting
this feature.
Anyway, both 8259 models do support 8080 -- somehow I was able to use
this combination in the past.
> > > the 8085 or the 8088 mode. The 'A' version and subsequent CMOS versions
> > > provided a LTIM bit in the initialization register, ICW1 (bit 3). The
> > > function of this bit is to prevent resetting the input latch when an EOI
> > > (specific or non-specific) if sent to the device, IF the interrupt request
> > > line is still true. This has the effect of allowing a level to be
> > > detected. With this, multiple interrupt requests may be ORed into the same
> > > IRQ line.
> >
> > You are writing of an INTA cycle for sure.
>
> No. INTA comes from the CPU. Writing the EIO comes from the port, i.e.,
> 0x20 out port 0x20 by any means you want including the CPU.
Of course INTA comes from CPU. But it is INTA that is responsible for
clearing the respective input latch aka the IRR bit. EOI only clears ISR
and is irrelevant to IRR.
> Sure, sure, sure. You call my collegue a liar and then hide in the
> corner and cry. If you took the time to learn from your mistakes, you
> might know something. Johnson spent some considerable time and effort,
> reviewing his response with me, to show you how these very old devices
> worked.
Hmm, I spent a considerable time reading 8259 and 8259A documentation.
For several years I programmed both chips for both 8080 and x86 systems
(including but not limited to mixed 8259A/APIC systems), including
specialized 8259 evaluation boards (i.e. using oscilloscope and multimeter
equipment). Both my readings and my experiences agree with each other and
are presented here. Unfortunately both of them disagree with what I read
from your collegue.
There is a possibility my description is not clear enough though opinions
of other people seem to suggest it is not the case. In no case I call
your collegue a liar -- I understand he actually believes in what he
writes. It just happens he is wrong or just misses some bits, which is
not unusual for a human and it is sometimes difficult for one to realize
it. On the other hand I cannot see why can't just Richard or you read the
docs or test real chips.
By no means I want to hide in the corner -- I just believe our discussion
brings nothing new to linux-kernel and may actually confuse people which
do not know 8259A very well and hope to learn something reading this list.
Maciej
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
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