UDMA Problem on VIA chipset - K7M motherboard

From: Marco Meloni (tonno@stud.unipg.it)
Date: Mon Feb 21 2000 - 12:03:13 EST

I have a Asus k7m mb with amd athlon 500 processor.
When I try to enable DMA on hda using hdparm -d 1 I get the following
errors:

hda: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hda: dma_intr: error=0x84 { DriveStatusError BadCRC }
hda: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hda: dma_intr: error=0x84 { DriveStatusError BadCRC }
hda: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hda: dma_intr: error=0x84 { DriveStatusError BadCRC }
hda: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hda: dma_intr: error=0x84 { DriveStatusError BadCRC }
hda: DMA disabled
ide0: reset: success

-------

a few configuration that may be of some help:

Drive info:

 
/dev/hda:
 
 Model=QUANTUM FIREBALLlct08 08, FwRev=A05.0X00, SerialNo=692935959353
 Config={ HardSect NotMFM HdSw>15uSec Fixed DTR>10Mbs }
 RawCHS=16383/16/63, TrkSize=32256, SectSize=21298, ECCbytes=4
 BuffType=3(DualPortCache), BuffSize=418kB, MaxMultSect=16,
MultSect=16
 DblWordIO=no, OldPIO=2, DMA=yes, OldDMA=2
 CurCHS=16383/16/63, CurSects=16514064, LBA=yes, LBAsects=16514064
 tDMA={min:120,rec:120}, DMA modes: mword0 mword1 mword2
 IORDY=on/off, tPIO={min:120,w/IORDY:120}, PIO modes: mode3 mode4
 UDMA modes: mode0 mode1 mode2 mode3 *mode4

Kernel booting messages about via:

VP_IDE: IDE controller on PCI bus 00 dev 21
VP_IDE: not 100% native mode: will probe irqs later
Split FIFO Configuration: 8 Primary buffers, threshold = 1/2
                           8 Second. buffers, threshold = 1/2
    ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio
ide0: VIA Bus-Master (U)DMA Timing Config Success
    ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:DMA, hdd:pio
ide1: VIA Bus-Master (U)DMA Timing Config Success

cat of proc - via file:
^
Command register = 0x7
Master Read Cycle IRDY 0 Wait State
Master Write Cycle IRDY 0 Wait State
FIFO Output Data 1/2 Clock Advance: off
Bus Master IDE Status Register Read Retry: on
Latency timer = 32 (max. = 0)
Interrupt Steering Swap: off
------------------Primary IDE------------Secondary IDE-----
both channels togth: yes yes
Prefetch Buffer : on on
Post Write Buffer: on on
FIFO Conf/Chan. : 08 08
Threshold Prim. : 1/2 1/2
Read DMA FIFO flush: on on
End Sect. FIFO flush: on on
Max DRDY Pulse Width: No limitation
Bytes Per Sector: 512 512
--------------drive0------drive1-------drive0------drive1----
DMA enabled: yes no yes no
Act Pls Width: 03 11 03 11
Recovery Time: 01 09 01 09
Add. Setup T.: 4T 4T 4T 4T
------------------UDMA-Timing-Control------------------------
Enable Meth.: 1 0 1 0
Enable: yes no yes no
Transfer Mode: PIO DMA PIO DMA
Cycle Time: 2T 5T 2T
5T

---
Pci chipset id:

pci bus 0x0 cardnum 0x04 function 0x0000: vendor 0x1106 device 0x0686
 VIA Device unknown
 
pci bus 0x0 cardnum 0x04 function 0x0001: vendor 0x1106 device 0x0571
 VIA Device
unknown

Ciao,
Marco. 

--
A volte mi piacerebbe tornare indietro / la' dove e' rimasta la vita
correre coi pattini sulle rive dell'oceano / giocare con lei finche'
non sara' finita

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This archive was generated by hypermail 2b29 : Wed Feb 23 2000 - 21:00:28 EST