* Andre Hedrick <andre@linux-ide.org> [000518 20:23]:
>
> Drop a tuning patch on it first and see if it corrects the issue
> Expecially if it is an IronGate North Bridge and VIA South Bridge pair.
Indeed i have this exact chipset. I applied the patch from hedrick/ on
kernel.org. Now I get on bootup
AMD IronGate
Chipset Core ATA-66
Split FIFO Configuration: 16 Primary buffers, threshold = 1/2
0 Second. buffers, threshold = 1/2
ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio
ide0: VIA Bus-Master (U)DMA Timing Config Success
ide1: VP_IDE Bus-Master DMA disabled (FIFO setting)
ide1: VIA Bus-Master Config Success. No DMA Enabled
hda: Maxtor 91021U2, ATA DISK drive
hdc: CD-540E, ATAPI CDROM drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
ide1 at 0x170-0x177,0x376 on irq 15
hda: Maxtor 91021U2, 9770MB w/512kB Cache, CHS=1245/255/63, UDMA(33)
Partition check:
hda: hda1 hda2 hda3 < hda5 > hda4
Again I run the bonnie++ benchmark and the situation improoved alot. It
took over an hour to crash (in the same hard, silent way than before) in
comparison to a little over 3 Minutes without the patch.
I put append="splitfifo=1" into my lilo.conf and get this output of
/proc/ide/via:
petrus:~# cat /proc/ide/via
Command register = 0x7
Master Read Cycle IRDY 0 Wait State
Master Write Cycle IRDY 0 Wait State
FIFO Output Data 1/2 Clock Advance: off
Bus Master IDE Status Register Read Retry: on
Latency timer = 32 (max. = 0)
Interrupt Steering Swap: off
------------------Primary IDE------------Secondary IDE-----
both channels togth: yes yes
Prefetch Buffer : on off
Post Write Buffer: on off
FIFO Conf/Chan. : 16 00
Threshold Prim. : 1/2 1/2
Read DMA FIFO flush: on off
End Sect. FIFO flush: on off
Max DRDY Pulse Width: No limitation
Bytes Per Sector: 512 512
--------------drive0------drive1-------drive0------drive1----
DMA enabled: yes no yes no
Act Pls Width: 15 11 01 11
Recovery Time: 01 09 04 09
Add. Setup T.: 4T 4T 4T 4T
------------------UDMA-Timing-Control------------------------
Enable Meth.: 0 0 1 0
Enable: no no no no
Transfer Mode: PIO DMA DMA DMA
Cycle Time: 2T 5T 2T 5T
Does this make sense? I did not understand everything of the
comments in drivers/block/via82cxxx.c due to language problems.
What else can I do? Does the optimazation work as it is supposed to?
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This archive was generated by hypermail 2b29 : Tue May 23 2000 - 21:00:16 EST