Re: dcache-ac6-D - dcache threading

From: Andrey Savochkin (saw@saw.sw.com.sg)
Date: Mon Jun 05 2000 - 06:01:27 EST


On Mon, Jun 05, 2000 at 06:37:43PM +0900, kumon@flab.fujitsu.co.jp wrote:
> Andrey Savochkin writes:
> > > near line 1520 in eepro100.c:
> > > do {
> > > HERE>>> status = inw(ioaddr + SCBStatus);
> > > /* Acknowledge all of the current interrupt sources ASAP. */
> > > /* Will change from 0xfc00 to 0xff00 when we start handling
> > > FCP and ER interrupts --Dragan */
> > > outw(status & 0xfc00, ioaddr + SCBStatus);
> >
> > Are you able to estimante the time of this inw() per call?
[snip]
>
> Speedo interrupt handling frequecy:
> speedo_interrupt calls 33.7K/s
> "do{}" execution 71.5K/s
>
> These values mean the do{}-loop is executed 2.16 times per function
> call.
>
> At that moment, the WebBench transaction speed may be over 3500
> tran/s, but I forget to measure the exact value.
>
> Following values are that you requested:
> lock aquire 280ns/call
> movzwl(inw) 1580ns/call or 750ns/loop

Seems to be too long, even if assume a synchronous PCI transaction (it's
about 22 PCI cycles on 33MHz PCI). I don't know how to explain it.

> lock release 230ns/call
>
> FYI: 1 CPU clock is 2.2ns@450MHz
> lock aquire: if (test_and_set_bit(0, (void*)&sp->in_interrupt)) {
> lock release: clear_bit(0, (void*)&sp->in_interrupt);
>
> Huum, "movb" instruction should be applied to exit-lock, again.

You may remove this lock altogether. It's a pure debugging stuff.

> Is it enough for you?

Yes, that's very interesting data. Thank you.

Best regards
                                        Andrey V.
                                        Savochkin

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