On Wed, Jun 21, 2000, Vito Caputo <swivel@gnugeneration.com> wrote:
>>
>> A "HOSE" is a primary PCI bus. There are Alphas with 2, 4, and now 8
>> or more. We'd like to allow graphics cards to be placed on *any* of
>> those PCI buses and still work. In addition, we've now got a core
>> logic chipset (northbridge/southbridge) that supports AGP 4X, but it
>> looks like another bus, not just part of an existing bus.
>>
>> Ah, the wonders of a 64-bit address space... ;-}
>>
>
>I think intel / x86 has this now too, I've recently seen advertised x86
>systems
>with: 'Two 550Mhz Intel Pentium III Xeon & Intel 82443 GX+ Chipset
processors'
>also stating 'dual peer PCI buses'. I'm not an x86 hardware jockey but I
>assume this is similar to what you are referring to on alpha.
So if I understand correctly, that means that the problem we have with
the Apple Uni-N chipset is similar to what happens on Alpha and
potentially on those new x86 machines, which resumes to having more than
one PCI root (and so more than one complete PCI hierarchy, each one
having its own bus 0, bridges, etc...).
This is linux-kernel related, so I'm CC'ing to the kernel mailing list.
The way this is currently handled in Alpha is to remap everything and re-
assign new bus numbers in order for them to be unique (and so "fake" a
single root hierarchy). (Tell me if I'm wrong). I was thinking about
implementing a similar mecanism for PPC, but now that we are also having
x86 platforms with this problem, wouldn't it be better to re-design
enough of Linux kernel PCI layer so that it can handle several separate
busses (and so, several roots ?). This would require identifying them
with an additional info in pci_dev (inside the kernel) and extending /
proc/bus/pci significantly however.
Ben.
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