On Sat, 9 Dec 2000, Alan Cox wrote:
> > If/When x86 (or all?) architectures use this, will it make sense to
> > remove the PCI space cache line setting from drivers ?
> > Or is there borked hardware out there that require drivers to say
> > "This cacheline size must be xxx bytes, anything else will break" ?
>
> If there is surely the driver can override it again before enabling the
> master bit or talking to the device ?
Configuring PCI cacheline size with a value that is a multiple of the
right value should not break. MWIs will still write whole cache lines and
MRL and MRM may prefetch more data but this should be harmless.
But, configuring a device for a value lower that the right value of the
cache line size will break if the hardware actually invalidate cache-lines
on MWI. Bridges that alias MWI to MW will obviously not be harmed by such
a misconfiguration.
As a result, in my opinion:
- A device that requires some non zero cache line size value lower than
the right value for a given system and that actually use MWIs must not be
supported on that system, unless we know that the bridge does alias MWI to
MW. (If such a device can be configured for not using MWI, any value for
the PCI cache line size will not break).
- A driver that blindly shoe-horns some value for the cache-line size must
be fixed. Basically, it should not change the value if it is not zero and,
at least, warn user if it has changed the value because it was zero.
What are the strong reasons that let some POST softwares not fill properly
the cache line size of PCI devices ?
Gérard.
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This archive was generated by hypermail 2b29 : Fri Dec 15 2000 - 21:00:17 EST