Ralf Baechle <ralf@conectiva.com.br> writes:
> On Thu, Jan 11, 2001 at 12:56:57AM +0100, David Weinehall wrote:
>
> > > The MMU on these systems is a CAM, and the mmu table is thus backwards to
> > > convention. (It also means you can notionally map two physical addresses to
> > > one virtual but thats undefined in the implementation ;))
> >
> > Are there any other (not yet supported) platforms with similar (or other
> > unrelated, but hard to support because of the current architecture of
> > the kernel) problems?
> >
> > (No, I have no secret trumps up my sleeve, I'm just curious.)
>
> Having a reverse mappings is the least sucky way to handle virtual aliases
> of certain types of MIPS caches.
Hmm. I would think that increasing the logical page size in the kernel would
be the trivial way to handle virtual aliases. (i.e.) with a large enough page
size you can't actually have a virtual alias.
You could also play some games with simply allocating pages only with the proper
proper high bits. These games might also be useful on architectures for L2 caches
who have significant physical bits than PAGE_SHIFT bits.
But how does a reverse mapping help to handle virtual aliases? What are those
caches doing? The only model in my head is having a virtually indexed cache
where you have more index bits than PAGE_SHIFT bits.
Eric
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This archive was generated by hypermail 2b29 : Mon Jan 15 2001 - 21:00:34 EST