Are there any large-memory machines that need pci_alloc_consistent() in the
USB controller driver? If not, then let's just set up an uncached mapping
of all of DRAM and use a modified version of virt_to_bus and bus_to_virt.
It gets around all the issues of having a better allocator of uncached
memory. Even with a slab allocator for uncached memory, modified versions
of virt_to_bus and bus_to_virt would have to be used.
The other choice is cache invalidation and flushing around all the code that
touches ED's and TD's. This might not be too bad if it is encapsulated in
_read and _write macros. How performance critical is the ED and TD code?
The latest ARM -NP patches work on SA1110 with the SA1111 controller (which
is OHCI-like). With minimal tweaks they work on SA110/Footbridge with an
OHCI controller. We will be submitting these patches as tweaks. It's not
beautiful, but it doesn't change the mainstream (x86) code significantly.
Jamey
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This archive was generated by hypermail 2b29 : Thu Mar 15 2001 - 21:00:10 EST