Hello world,
Dave Jones' recent 2.4.2ac17 patch to mtrr.c to support the Cyrix III
unfortunately broke the AMD Athlon support. Here's a patch to correct
the problem (Dave must have overlooked the fall-through logic of the
switch statement).
Enjoy...
-- Troels Walsted Hansen--- mtrr.c1.38 Sun Mar 11 13:42:30 2001 +++ mtrr.c Mon Mar 12 21:02:15 2001 @@ -235,6 +235,12 @@ v1.38 20010309 Dave Jones <davej@suse.de> Add support for Cyrix III. + + v1.39 + 20010312 Troels Walsted Hansen <troels@thule.no> + Fixed the AMD Athlon support that Dave Jones' patch broke. + Also updated the version number to match this changelog. + */ #include <linux/types.h> #include <linux/errno.h> @@ -274,7 +280,7 @@ #include <asm/hardirq.h> #include <linux/irq.h> -#define MTRR_VERSION "1.37 (20001109)" +#define MTRR_VERSION "1.39 (20010312)" #define TRUE 1 #define FALSE 0 @@ -1964,6 +1970,14 @@ get_mtrr = intel_get_mtrr; set_mtrr_up = intel_set_mtrr_up; switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_CENTAUR: + /* Cyrix III has Intel style MTRRs, but doesn't support PAE */ + if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 6) { + size_or_mask = 0xfff00000; /* 32 bits */ + size_and_mask = 0; + } + break; + case X86_VENDOR_AMD: /* The original Athlon docs said that total addressable memory is 44 bits wide. @@ -1982,13 +1996,7 @@ size_and_mask = ~size_or_mask & 0xfff00000; break; } - case X86_VENDOR_CENTAUR: - /* Cyrix III has Intel style MTRRs, but doesn't support PAE */ - if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 6) { - size_or_mask = 0xfff00000; /* 32 bits */ - size_and_mask = 0; - } - break; + /* NOTE: fallthrough to default here! */ default: /* Intel, etc. */ - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Thu Mar 15 2001 - 21:00:14 EST