daniel sheltraw wrote:
> Hello kernel listees
> I have a busmaster question I am hoping you can help me with.
> If a PCI device is acting as a busmaster and the processor initiates a
> read/write to another device on the PCI bus while the busmater-device is in
> control of the bus what happens to the instructions initiated by the
> processor? Are they never seen by the device that the processor
> is trying to read/write?
An excellent book about PCI is Mindshare's "PCI System Architecture"
Third (or later?) Edition.
In the scenerio you outlined, the device currently holding the bus
would continue until it's latency timer expired (if it already hadn't),
stalling the CPU,
then the master which has been granted access next to the bus would
start it's access. If the only other master requesting access is the CPU,
then it will get it. If there are others, then it is implementation dependent
who has highest arbitration priority.
Note that since main memory is not on the PCI bus, the CPU can cary on
unless it tries to access video memory, IDE registers, etc. for IO.
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This archive was generated by hypermail 2b29 : Mon Apr 30 2001 - 21:00:20 EST