On Mon, 30 Apr 2001, Jeff Garzik wrote:
> "Richard B. Johnson" wrote:
> > Observe that the PCI DWORD (long) register at DWORD offset 15 consists
> > of 4 byte-wide registers (from the PCI specification), Max_lat, Min_Gnt,
> > Interrupt pin, and interrupt line. Nothing has to fit into 4 bits, you
> > have 8 bits. I haven't looked at the Linux code, but if it provides only 4
> > bits for the IRQ, it's broken.
> Non-IO-APIC Via audio hardware only decodes the lower 4 bits of the IRQ.
Woof... More GAWDAUFULL junk. You mean that if I write 0xff to the R/W
interrupt line register and read it back, it's only 0x0f? This didn't
save any money. There are only 4 interrupt 'pins', i.e., interrupt lines
that go to the PCI bus (A thru D). What these lines connect to for
actual IRQs is known only to the motherboard manufacturer hence the
BIOS has to check the pin value and write the appropriate IRQ value
into the interrupt line register. This register is used only as a
scratch-pad so that a driver "knows" what IRQ goes to the board. The
board, itself, never accesses this register. The board only gets one
interrupt connected (A thru D), and to the board, all interrupts are
So, if the driver can find by some other means, the interrupt that is
connected to the board, it can use that interrupt rather than something
that was written to the scratch register by the BIOS.
Penguin : Linux version 2.4.1 on an i686 machine (799.53 BogoMips).
"Memory is like gasoline. You use it up when you are running. Of
course you get it all back when you reboot..."; Actual explanation
obtained from the Micro$oft help desk.
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to email@example.com
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Mon Apr 30 2001 - 21:00:25 EST