Hi,
On Mon, Aug 06, 2001 at 03:00:07PM -0400, Richard B. Johnson wrote:
[snip]
> This may not be a timing problem, but rather a problem that was
> attempted to be fixed with some timing change.
>
> Possible problem (and solution). Given:
>
> writel(value, pci_reg);
> status = readl(pci_reg);
>
> The second readl() may (read will) complete before the writel().
> This is because writes to the PCI bus may be posted (queued). The
> first read will force all writes to complete, however the value
> read may be something that was not yet affected by the write.
>
> writel(value, pci_reg);
> status = readl(pci_reg);
> status = readl(pci_reg);
Thanks for the note, I'll keep it in mind.
However, for this particular case I'm interested about a loop like
while((a = readb(reg)) && --count >= 0);
I wonder if there are circumstances in which the repeated read's can return
"cached" values or whatever, so that the loop will result in significantly less
number of bus cycles than it's supposed?
My understanding is that there shouldn't be such.
Best regards
Andrey
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Tue Aug 07 2001 - 21:00:43 EST