On Wed, Sep 26, 2001 at 10:44:14AM -0700, Linus Torvalds wrote:
> Do you have an actual SMP Athlon to test? I'd love to see if that "locked
> add" thing is really SMP-safe - it may be that it's the old "AMD turned
> off the 'lock' prefix synchronization because it doesn't matter in UP".
> They used to have a bit to do that..
Same, my dual reports:
[bcrl@toomuch ~]$ ./a.out
nothing: 11 cycles
locked add: 11 cycles
cpuid: 68 cycles
Which is pretty good.
> That said, it _can_ be real even on SMP. There's no reason why a memory
> barrier would have to be as heavy as it is on some machines (even the P4
> looks positively _fast_ compared to most older machines that did memory
> barriers on the bus and took hundreds of much slower cycles to do it).
I had discussions with a few people from intel about the p4 having much
improved locking performance, including the ability to speculatively
execute locked instructions. How much of that is enabled in the current
cores is another question entirely (gotta love microcode patches).
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This archive was generated by hypermail 2b29 : Sun Sep 30 2001 - 21:00:47 EST