>Intel's p3/4 prefetch instructions are hints only. They are only executed
>asynchronously, and depend heavily on the other load on the processor at
>the time. They are not required to prefetch, *and* they are not required
>to be executed when you think they should in the flow of the program. You
>can serialize them by using an MFENCE instruction, but they still aren't
>guaranteed to run.
>Check the p4 manuals. In fact, I'm not sure prefetch was implemented in
>p3. I could be wrong, check the manual.
PREFETCHx are in P3. I am aware that processor executes them optionally.
MFENCE may be a good idea. If load/store queues are full the processor
may just drop the prefetch instruction. I should try this.
Thanks for the suggestion. /bulent
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This archive was generated by hypermail 2b29 : Sun Sep 30 2001 - 21:00:57 EST