>Hrm... this makes me wonder if the Byte Merge option is keeping the PCI
>consistancy rules, or perhaps the aic7xxx driver is making assumptions
>about when PCI writes are actually occuring, without doing a read cycle
>between critical writes to make sure they actually happen.
See my other post on this subject. The driver knows that a read is
required to ensure that a write is posted, but assumes that 8bit
transactions are forwarded as such, writes are issued in the order
retired (we use a memory barrier to avoid the compiler using a
different order), and that reads cannot pass posted writes.
-- Justin - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to firstname.lastname@example.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Sun Sep 30 2001 - 21:01:12 EST