Re: [PATCH] Pentium IV cacheline size.

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> Currently, we're using a L1_CACHE_SHIFT value of 7
> for Pentium 4, which equates to 128 byte cache lines.
> Curious, I dumped the info on the only P4 I could find,
> and noticed they were 64 byte.

the value is correct, but the name should be SMP rather than L1,
since we (only?) use the value for aligning data to avoid false sharing.

regards, mark hahn

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• Next message: Tobias Hahn: "Kernel compile error"
• Previous message: Paul E. McKenney: "Re: Re: RFC: patch to allow lock-free traversal of lists with insertion ^M"
• In reply to: Dave Jones: "[PATCH] Pentium IV cacheline size."
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