In article <9s82rl$k51$1@cesium.transmeta.com>,
H. Peter Anvin <hpa@zytor.com> wrote:
>
>Is using %cr2 really faster than the old implementation, or is there
>another reason? It seems that the alignment constraints on the stack
>still remains, since the %esp solution still remains in places...
I think the _real_ issue with that patch is that %cr2 is by no means
architecturally even guaranteed to work the way the patches want it to
work.
It's simply not a general-purpose register, and I don't see why it is
assumed to be (a) fast (b) stable and (c) writable.
I could well imagine a x86-compatible chip where %cr2 isn't even
writable. In fact, reading the intel documentation, I see _nowhere_ a
mention of %cr2 being writable at all - it all just says "contains the
fault address".
Similarly, there is _nothing_ that guarantees that the low bits of %cr2
are meaningful, writable, or even implemented.
Which means that the whole approach is just depending on undocumented
implementation behaviour. That's asking for trouble.
Linus
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This archive was generated by hypermail 2b29 : Wed Nov 07 2001 - 21:00:31 EST