Re: highmem, aic7xxx, and vfat: too few segs for dma mapping

From: Jens Axboe (
Date: Wed Dec 12 2001 - 04:36:54 EST

On Tue, Dec 11 2001, Gérard Roudier wrote:
> On Mon, 10 Dec 2001, David S. Miller wrote:
> > From: Gérard Roudier <>
> > Date: Mon, 10 Dec 2001 20:21:21 +0100 (CET)
> >
> > Btw, a 16 MB boundary limitation would have no significant impact on
> > performance and would have the goodness of avoiding some hardware bugs not
> > only on a few Symbios devices in my opinion. As we know, numerous modern
> > cores still have rests of the ISA epoch in their guts. So, in my opinion,
> > the 16 MB boundary limitation should be the default on systems where
> > reliability is the primary goal.
> >
> > Complications arrive when IOMMU starts to remap things into a virtual
> > 32-bit bus space as happens on several platforms now.
> >
> > Jen's block layer knows nothing about what we will do here, since
> > he only really has access to physical addresses.
> >
> > Only after the pci_map_sg() call can you inspect DMA addresses and
> > apply such workarounds.
> Such workaround will add bloat on the already bloated for no relevant
> reason 'generic scatter to physical' thing.
> As you know, low-level drivers on Linux announce some maximum length for
> the sg array. As you guess, in the worst case, each sg entry may have to
> be cut into several real entry (hoped 2 maximum) due to boundary
> limitations. At a first glance, low-level drivers should announce no more
> than half their real sg length capability and also would have to rewalk
> the entire sg list.

That's why these boundary limitations need to be known by the layer
build the requests for you.

> I used and was happy to do so when the scatter process was not generic.
> If we want it to be generic, then we want it to do the needed work. If
> generic means 'just bloated and clueless' then generic is a extreme bad
> thing.
> 'virt_to_bus' + 'flat addressing model' was the 'just as complex as
> needed' for DMA model and most (may-be > 99%) of existing physical
> machines are just happy with such model. The DMA/BUS complexity all O/Ses
> have invented nowadays is a useless misfeature when based on the reality,
> in my opinion. So, I may just be dreaming, at the moment. :-)
> If one really wants for some marketing reason to support these ugly and
> stinky '32 bit machines that want to provide more than 4GB of memory by
> shoe-horning complexity all over the place', one should use his brain,
> when so-featured, prior to writing clueless code.

First of all, virt_to_bus just cannot work on some archetectures that
are just slightly more advanced than x86. I'm quite sure Davem is ready
to lecture you on this.

Second, you are misunderstanding the need of a page/offset instead of
virtua_address model. It's _not_ for > 4GB machines, it's for machines
with highmem. You'll need this on the standard kernel to I/O above
860MB, that that is definitely a much bigger part of the market. Heck,
lots of home users have 1GB or more with the RAM prices these days.

Jens Axboe

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