On Fri, 4 Jan 2002 13:12:44 +0100 (MET), Maciej W. Rozycki wrote:
> Still the
>APIC looks insane for me -- it should really signal an error only once an
>interrupt is received, like it does for interrupts from remote sources.
But a remote interrupt source supplies a vector, doesn't it? If we
assume that the local APIC checks the vector on arrival _of_the_vector_,
then it does make some sense that it also flags a null vector written
to one of the LVT entries as an error. The bug really is that it forgets
to take the mask bit into account. However, the behaviour _is_ there and
we have to avoid triggering it.
>> + if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
>> + apic_write(APIC_ESR, 0);
>
> Use apic_write_around() instead as the 11AP workaround -- it was
>introduced specifically for this purpose. Using anything else doesn't
>guarantee no back-to-back APIC writes due to interrupts (specifically
>writes to the EOI register).
I disagree. The write doesn't occur on P5s, so 11AP doesn't apply.
If I had used an unconditional write_around() instead, then someone
would complain that I'm violating erratum 3AP (even though it doesn't
matter in this case). The test as written unambiguously handles both
3AP and 11AP, and is identical to the "clear ESR" code in
setup_local_APIC() around line 385.
/Mikael
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This archive was generated by hypermail 2b29 : Mon Jan 07 2002 - 21:00:25 EST