Justin Carlson wrote:
> On Wed, 2002-01-16 at 14:49, R. Sinoradzki wrote:
>
>>O.K my question:
>>Consider two modern processors that share some data and a lock.
>>The lock may be implemented with something like an atomic test-and-set
>>instruction. Now processor 'A' acquires the lock and works with the data.
>>Processor 'B' also wants to access the data, but internally reorders it's
>>instructions because the instructions seem independent from each other.
>>So 'B' might access the data without having the lock.
>>If it's a single processor system, reordering instructions in a way that
>>ensures that it looks 'as if' everything has been executed in the right order
>>might be easy, but in a multiprocessor system 'A' doesn't know 'B's state.
>>
>
> Then you've got a bug. Modern implementations that do SMP provide some
> way of placing barriers around speculative execution structures to make
> sure you don't, say, go out and read some memory location that changes
> state in a device because that's an OK speculative action to take.
>
> Can't really comment on x86, as I'm not very good with it, but taking
> for example MIPS and Alpha, in addition to the ll-sc ops, there are a
> sync and mb instructions, respectively, which provide a method for
> assuring that previous operations have become visible in terms of
> general machine state before going on.
>
> -Justin
>
Ah, thank you for the keywords.
Sorry, I should have searched "multiprocessor synchronization" in Google, but
I tried something else that gave me a lot of useless results ...
Ralf
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This archive was generated by hypermail 2b29 : Wed Jan 23 2002 - 21:00:17 EST