I brought this to the list once about a half a year ago. One item I got
in feedback was that
it would require a reverse-mapping allocator (for the cases of mappings
to ram) to be able to coalesce/rearrange pages to
make room for contiguous 4M pages. Such an allocator now exists...
search an LKML archive for "rmap".
In the case of non-swappable memory, the allocator is not an issue. In
fact the kernel does use 4M pages to map the kernel itsself
(non-swappable and contiguous) and the 1:1 mapping of physical memory on
non-himem kernels.(not 100% sure about that part) I immagine this could
be easily extended to things like the bt848, the framebuffer on all
video cards (ok not ISA-VGA), and any mmio regions sufficiently large
enough. ( or redo BIOS PCI setup so regions are at least 4M apart...)
As for reduced TLB misses... I just read the specs for decoding the MSRs
on AMD processors to determine cache organization, and it turns out that
they have separate TLBs for 4k vs 4M pages. So you actually get more TLB
entries by using 4M pages...
Now I guess we need to start thinking about extent based filesystems and
how to page in/out 4M pages...mmap files...
Yinlei Yu wrote:
> Hi,
>
> I am working on a project that keep accessing lots of memory
> randomly(say 500MB-1.5GB) and we do have such amount of memory
> installed so there's almost no page faults while running the entire
> program. Since x86 architecutre has a 4M page feature, is it possible
> to make use of these big pages instead of 4K pages in my program (a
> user-level application) so I can expect much fewer TLB misses due to
> the reduced number of TLB entries? Thanks very much!
>
>
>
>
>
>
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This archive was generated by hypermail 2b29 : Wed Jan 23 2002 - 21:00:24 EST