On Sun, 20 Jan 2002, Manfred Spraul wrote:
> > #define SPURIOUS_APIC_VECTOR 0xff
> > #define ERROR_APIC_VECTOR 0xfe
> > #define INVALIDATE_TLB_VECTOR 0xfd
> > #define RESCHEDULE_VECTOR 0xfc
> > -#define CALL_FUNCTION_VECTOR 0xfb
> > +#define TASK_MIGRATION_VECTOR 0xfb
> > +#define CALL_FUNCTION_VECTOR 0xfa
> >
> Are you sure it's a good idea to have 6 interrupts at priority 15? The
> local apic of the P6 has only one in-service entry and one holding
> entry for each priority.
we havent been following this strict rule for some time. We are
distributing device interrupts according to this rule, but only as an
optimization, and only as long as the number of IRQ sources is smaller
than ~30.
i think the worst-case is that we might lose a local APIC timer interrupt
- and this only on older APIC versions. Recent CPUs should handle this
correctly. AND, we have the local APIC timer interrupt on its own priority
level anyway.
So i think the P6 documentation is a pessimisation of the true situation,
and that we can very well have multiple interrupts on the same priority
level even on older APICs - as long as the local timer interrupt is not
amongst them.
Ingo
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This archive was generated by hypermail 2b29 : Wed Jan 23 2002 - 21:00:39 EST