From: Reid Hekman <reid.hekman@ndsu.nodak.edu>
Date: 21 Jan 2002 04:53:39 -0600
As I have a couple systems that may/may not be affected, I'm seeking
some clarification. Is this an effect of the errata published by AMD in
the Athlon models 4 & 6 revision guides as "INVLPG Instruction Does Not
Flush Entire Four-Megabyte Page Properly with Certain Linear Addresses"?
That errata lists all Athlon Thunderbirds as affected and all Athlon
Palominos except for stepping A5.
Regardless of specific errata listings, will future workarounds be
enabled based on cpuid or via a test for the bug itself?
The funny part is, if this published errata is the problem, it cannot
be a problem under Linux since we never invalidate 4MB pages. We
create them at boot time and they never change after that.
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Wed Jan 23 2002 - 21:00:45 EST