From: Studierende der Universitaet des Saarlandes <masp0008@stud.uni-saarland.de>
Date: Wed, 23 Jan 2002 10:38:09 +0000
Then "nopentium" only works by chance: I assume that speculative
operations do not walk the page tables, thus the probability that a
valid TLB entry is found for the GART mapped page is slim. But if there
is an entry, then the corruption would still occur.
This isn't true. The speculative store won't get data into the
cache if there is a TLB miss.
4MB pages map the GART pages and "other stuff", ie. memory used by
other subsystems, user pages and whatever else. This is the only
way the bug can be thus triggered for kernel mappings, which is why
turning off 4MB pages fixes this part.
The only unresolved bit is the fact that we map these GART pages
cacheable into user space. That ought to cause the problem too.
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