From: David Mosberger <davidm@hpl.hp.com>
Date: Mon, 11 Feb 2002 19:18:38 -0800
Let's see: on Itanium, a ld takes up an M slot and has a 2 cycle
access latency (if in the first level cache). This may or may not be
noticable in benchmarks, but it certainly won't go faster. And all
this just for task coloring (which we can do with the old set up just
fine)?
The compiler will schedule the latency out of existence.
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