Richard B. Johnson wrote:
>
> Yeh? Then "how do it know?". It doesn't. I/O instructions are ordered,
> however, that's all. There is no bus-interface state machine that exists
> except on the addressed device. The CPU driven interface device just
> makes sure that the data is valid before the address and I/O-read or
> I/O-write are valid after this. The address is decoded by the device
> and is used to enable the device. It either puts its data onto the
> bus in the case of a read, or gets data off the bus, in the case of
> a write. The interface timing is specified and is handled by hardware.
> In the meantime the CPU has not waited because there is nothing to
> wait for. On a READ, if the device cannot put its data on the bus
> fast enough, it puts its finger io IO-chan-ready. This forces the
> CPU (through its bus-interface) to wait.
>
> Writes to nowhere are just that, writes to nowhere.
>
On the ISA bus, yes. The PCI and front side busses will be held in wait
until the transaction is completed.
The exact requirement is a bit more complicated, something along the
lines of "an SMI triggered in response to an OUT will be taken before
the OUT is retired."
-hpa
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This archive was generated by hypermail 2b29 : Fri Mar 15 2002 - 22:00:19 EST