> And it is left up to the arch in my patch, I've simply imposed a little more
> order on what, up till now, has been a pretty chaotic corner of the kernel,
> and provided a template that satisfies a wider variety of needs than the old
Yep, got that - just reenforcing the point.
> It sounds like the table translation you're doing in the hypervisor is
> exactly what I've implemented in the kernel. One advantage of going with
> the kernel's implementation is that you get the benefit of improvements
> made to it, for example, the proposed hashing scheme to handle extremely
> fragmented physical memory maps.
I should clarify a bit -- we run on two different hypervisor
interfaces. The iSeries interface leaves this translation work to the
OS. In that case Linux has an array translation lookup which is
analogous to your patch. We just managed to hide everything in
arch/ppc64 by doing this lookup when inserting hashed page table and I/O
table mappings. Other than at that low level, the remappings are
transparent to Linux -- it just sees a nice big flat physical address
On pSeries, the hypervisor does the translation work under the covers,
but as you point out, Linux doesn't get the chance to play with
different mapping schemes. Then again, that does simplify my life ...
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This archive was generated by hypermail 2b29 : Tue May 07 2002 - 22:00:14 EST