On Thursday 02 May 2002 02:20, Anton Blanchard wrote:
> > so ia64 is one of those archs with a ram layout with huge holes in the
> > middle of the ram of the nodes? I'd be curious to know what's the
> > hardware advantage of designing the ram layout in such a way, compared
> > to all other numa archs that I deal with. Also if you know other archs
> > with huge holes in the middle of the ram of the nodes I'd be curious to
> > know about them too. thanks for the interesting info!
> From arch/ppc64/kernel/iSeries_setup.c:
> * The iSeries may have very large memories ( > 128 GB ) and a partition
> * may get memory in "chunks" that may be anywhere in the 2**52 real
> * address space. The chunks are 256K in size.
> Also check out CONFIG_MSCHUNKS code and see why I'd love to see a generic
> solution to this problem.
Hmm, I just re-read your numbers above. Supposing you have 256 GB of
'installed' memory, divided into 256K chunks at random places in the 52
bit address space, a hash table with 1M entries could map all that
physical memory. You'd need 16 bytes or so per hash table entry, making
the table 16MB in size. This would be about .0006% of memory.
More-or-less equivalently, a tree could be used, with the tradeoff being
a little better locality of reference vs more search steps. The hash
structure can also be tweaked to improve locality by making each hash
entry map several adjacent memory chunks, and hoping that the chunks tend
to occur in groups, which they most probably do.
I'm offering the hash table, combined with config_nonlinear as a generic
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