Re: Memory Barrier Definitions

From: Alan Cox (
Date: Tue May 07 2002 - 15:27:04 EST

> forms of processor memory barrier instructions. It is _very_ expensive
> to blindly force all memory references to be ordered completely to the
> seperate spaces. The use of wmb(), rmb(), and mb() is overloaded in the
> context of PowerPC.

I think I follow

You have

        Compiler ordering
        CPU v CPU memory ordering
        CPU v I/O memory ordering
        I/O v I/O memory ordering

and our current heirarchy is a little bit more squashed than that. I'd
agree. We actually hit a corner case of this on the IDT winchip x86 where
we run relaxed store ordering and have to define wmb() as a locked add of
zero to the top of stack - which does have a penalty that isnt needed
for CPU ordering.

How much of this impacts Mips64 ?


To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

This archive was generated by hypermail 2b29 : Tue May 07 2002 - 22:00:31 EST