> Does this mean that this piece of memory does have to be declared
> uncacheable until DMA is finished ?
> How else do you solve th problem of validity during DMA and
> especially after DMA ?
>
> You flush either before/after depending upon whether the cpu caches
> are writeback in nature or not, and the cpu is not allowed to touch
> those addresses while the device is doing the DMA.
So we need some kind of cache_aligned macro in our USB data
structures if they contain a buffer. Which macro would we have to use ?
Is there a macro conditional to incoherent architectures so we don't
have to waste RAM needlessly ?
Regards
Oliver
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This archive was generated by hypermail 2b29 : Sat Jun 15 2002 - 22:00:16 EST