Hi!
> The DMA_ALIGN attribute doesn't work, on some systems the PCI
> cacheline size is determined at boot time not compile time.
>
> Another note, it could be per-PCI controller what this cacheline size
> is. We'll need to pass in a pdev to the alignment interfaces to
> do this correctly.
>
> So none of this can be done at compile time folks.
But upper bound is certainly known at compile time, right?
Pavel
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This archive was generated by hypermail 2b29 : Sat Jun 15 2002 - 22:00:26 EST