On Mon, 2002-08-05 at 09:12, Luca Barbieri wrote:
> So I'm only replacing the lock; addl $0,0(%%esp) with the Xfence
> instructions which are more efficient.
The original code has rmb not doing any kind of CPU operation, and wmb
likewise. (Quoting 2.4 and 2.5.29 here)
You don't need stronger barriers except on the Pentium Pro or the
Winchip because of the guarantees already made by the processor and by
the PCI interface.
The only case you need a store fence with non buggy/weird processors is
when you do non temporal stores. In that situation the barriers are
still not needed because the non temporal using functions already have
their own sfence instructions and need them.
#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":
:"memory")
#define rmb() mb()
#ifdef CONFIG_X86_OOSTORE
#define wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": :
:"memory")
#else
#define wmb() __asm__ __volatile__ ("": : :"memory")
#endif
For the PPro a lock addl is the most efficient one I know of for working
around the store order errata. If you want to optimise it further then
the winchip appears to be fractionally faster using an rdmsr() but that
impacts registers so wants more profiling
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This archive was generated by hypermail 2b29 : Wed Aug 07 2002 - 22:00:26 EST