On Mon, Aug 19, 2002 at 11:21:21AM -0700, Xuehua Chen wrote:
> Met a problem in my research. I run some code on a
> Xeon dual-processor machine. It seems to me that there is
> a cache coherence problem. As I am not so familiar
> to this topic, I would like to ask some experts about
> the following questions.
>
> 1. Do Xeon processors have hardware mechanisms to
> maintain cache coherence?
Yes, in usual closely coupled SMP systems.
> 2. Does the SMP kernel handle the cache coherence
> problem
In its own ways, yes. It is relying on hardware doing
it in major part.
> 3. What should I do if both of them don't handle cache
> coherence.
Report the issue with lots of technical details
on linux-smp@vger.kernel.org, and possibly continue
discussion there.
Data like:
- What machine, whose motherboard ?
- How much memory ?
- What steppings are the processors ? (not same ?)
- How you configured the kernel ?
(Not quite the entire .config file, just first
50 lines or so telling processor details.)
And most importantly:
- Describe why do you suspect there is cache-coherence
problem in the system ? In the kernel side, or
in your application ? How it is manifesting itself ?
> Thanks.
> Frank Samuel
/Matti Aarnio
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This archive was generated by hypermail 2b29 : Fri Aug 23 2002 - 22:00:17 EST