On Tue, 2002-09-17 at 13:39, David S. Miller wrote:
> From: john stultz <firstname.lastname@example.org>
> Date: 17 Sep 2002 13:29:18 -0700
> Some NUMA boxes do not have synced TSC, so on those systems your
> code won't work.
> It would have been really nice if x86 had specified a "system tick"
> register that incremented based upon the system bus cycles and thus
> were immune the processor rates.
Some systems do, if I'm understanding you properly. Summit based boxes
have an on-chipset performance counter that runs at 100Mhz. My
cyclone-timer patch uses this as a gettimeofday/__delay time source in
the 2.4 kernel. Additionally George Anzinger has patches that allow the
ACPI PM timer to be used as well. Intel's HPET should also provide
another time source.
> I foresee lots of patches coming which basically are "how does this
> x86 system provide a stable synchronized tick source".
True, but hopefully my timer-changes patch will allow for better
abstraction around these varied time sources, so one won't really need
to know how all of these different sources work.
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This archive was generated by hypermail 2b29 : Mon Sep 23 2002 - 22:00:20 EST