Re: [PATCH] Re: time() glitch on 2.4.18: solved

From: Richard B. Johnson (root@chaos.analogic.com)
Date: Tue Nov 05 2002 - 15:38:00 EST


On Tue, 5 Nov 2002, Willy Tarreau wrote:

> On Tue, Nov 05, 2002 at 08:07:26PM +0000, Alan Cox wrote:
> > On Tue, 2002-11-05 at 19:29, Richard B. Johnson wrote:
> > > The only hardware a modern PC needs to use "slow-down_io" on is
> > > the RTC CMOS device. Since we need to support older boards, you
> > > don't want to remove the _p options indiscriminately, but you do
> > > not want them ever between two consecutive writes to the same device-
> > > port.
> >
> > I own at least one that needs the _p on the DMA controller and at one
> > that needs _p on the PIT
>
> Well, in fact, Intel's 82C54 datasheet says that this chip needs at least
> 165 ns between two consecutive operations, either read or write. So with a
> 8 Mhz bus, you may effectively need to insert fake accesses, although most
> modern chipsets certainly have better specs.
>

Its not a clocked bus. The 8 MHz means nothing. It's an async bus
and if the setup timing of the data/address-decode/chip-select sequence
is not violated, you get ~200ns between accesses so chip-to-chip
select time comes automatically. But, some older motherboards violated
all kinds of specs. They did this deliberately so you could plug
RAM boards into the ISA bus and get reasonable performance. If we still
support them, you need some artifical waits.

> But the spec clearly states that you can interleave accesses to other
> counters between the first and second bytes without problem, so good
> implementations should see no side effect.
>
> Richard, if your PIT doesn't support accesses to port 80, could you try to
> use other ports ?
>
> Cheers,
> Willy
>

It's not the port address. It's the bus state. The chip requires two
consecutive writes when setting that latch. It's just like a 32-bit
write to a 32-bit port (like PCI access), you can't write to the
low-port, do something else, then write to the high port. It needs to be
done with no intervening bus states. In the AMD case, it's probably
because the address is ignored on the second write.

Cheers,
Dick Johnson
Penguin : Linux version 2.4.18 on an i686 machine (797.90 BogoMips).
   Bush : The Fourth Reich of America

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