On Mon, 11 Nov 2002, David S. Miller wrote:
> From: Hugh Dickins <hugh@veritas.com>
> Date: Mon, 11 Nov 2002 18:25:25 +0000 (GMT)
>
> On some architectures (cachetlb.txt gives HyperSparc as an example)
> it is essential to flush_cache_page while pte is still valid: the
> rmap VM diverged from the base 2.4 VM before that fix was made,
> so this error has crept back into 2.5.
> ...
> (I wonder, what happens if userspace now modifies the page
> after the flush_cache_page, before the pte is invalidated?)
>
> Thanks for catching this.
>
> On architectures that are affected (such as the mentioned HyperSPARC
> chips), the cpu will take a trap and OOPS the kernel if the PTE is
> invalidated before the cache flush is made.
Thanks for shedding light on that; but I'm still wondering if there
might be data loss if userspace modifies the page in the tiny window
between correctly positioned flush_cache_page and pte invalidation?
Hugh
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This archive was generated by hypermail 2b29 : Fri Nov 15 2002 - 22:00:24 EST