The attached represents an initial stab at implementing topology functions (or
actually indirecting topology through the subarchitecture features).
Getting this far made me realise that the current topology infrastructure is
rather inadequate (being geared towards the needs of NUMA machines).
All I really need for voyager is the concept of cpu_nodes (voyager CPU cards
have huge L3 caches and up to 4 CPUs each, so scheduling between CPU cards can
end up rather expensive in terms of cache invalidation). I have no use for
memory affinities since the voyager memory map is uniform.
I'd like to rework the current sysfs cpu/node pieces to provide two separate
topologies (one for CPU and one for memory).
Ultimately, the scheduler could be tuned to use the topologies to make
scheduling decisions. When that happens, we can probably fold the current
Pentium Hyperthreading stuff into a simple topology map as well.
I believe Martin Bligh and Bill Irwin are working (or at least thinking)
somewhat along these lines, so I thought I'd gather feedback before jumping
into a wholesale rewrite.
James Bottomley
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This archive was generated by hypermail 2b29 : Sat Nov 30 2002 - 22:00:23 EST